This invention relates to integrated circuits, and particularly to fabricating integrated circuits comprising an active transistor electrically connected to a drain junction of a trench capacitor by an overlying contact formed between the active transistor and another passive transistor.
Dynamic random access memory (DRAM) technology stores each bit of data in a separate capacitor. A DRAM cell includes a field effect transistor (FET) and a capacitor fabricated upon and within a semiconductor substrate. To meet the demand for integrated circuits with high integration densities and minimum feature sizes, trench capacitors have been developed for use in DRAM cells. Trench capacitors extend into the substrate of a DRAM cell rather than across the surface of the substrate and thus require little additional space.
Current DRAM cells include a buried strap for electrically connecting a drain region of a FET to the top of a trench capacitor that comprises doped polysilicon. Unfortunately, directly contacting the drain region to the trench capacitor may generate crystalline defects that can cause a relatively large leakage current to pass from the buried strap through the channel of the FET and to the source, thereby destroying the stored data. To prevent such leakage, a barrier layer can be formed between the strap/trench capacitor structure and the drain region of the FET. However, this barrier layer needs to be sufficiently thin to allow dopants to out diffuse and to allow current to flow through the barrier layer. Further, the presence of the barrier layer can undesirably increase the temperature required for this out-diffusion. However, at higher temperatures, the dopant diffusion can be so high that the FET experiences a change in its threshold voltage, VT.
An improved DRAM cell has been developed that includes silicide upon the surfaces of the buried strap, the trench capacitor, and the source and drain (source/drain) junctions of the FET. However, a barrier layer is still positioned at the edge of the buried strap that can lead to disconnect between the source/drain silicide and the capacitor silicide.